1. Field of the Invention
The present invention relates to a synchronous random access memory performing data access operation such as a data readout operation/a data writein operation in synchronism with a clock signal, and more particularly, it relates to a synchronous random access memory capable of performing a memory access cycle in which a data readout process, a data writein process, and a reset process are performed sequentially in order.
2. Description of the Prior Art
Recently, synchronous random access memories are widely used as cache memories incorporated in central processing units (CPU) and the like because the synchronous random access memories are very fitted to pipeline processes. In addition, because the synchronous random access memories are capable of absorbing a signal skew and they may be applied to higher speed systems, they are becoming one of the leading mainstreams of the memory field.
FIG. 1 is a diagram showing a configuration of a conventional synchronous random access memory described above. FIG. 2 is a timing chart showing the timing of the memory access operation of the conventional synchronous random access memory shown in FIG. 1.
The conventional synchronous random access memory shown in FIG. 1 has a most simple configuration in which the number of ports for each of the data output and data input is one. In FIG. 1, the memory array 101 comprises m.times.(n.times.d) memory cells (each of m, n, and d is a natural number). This character "m" designates the number of rows (or a row number) in the X direction and the character "n" denotes the number of column (or a column number) in the Y direction, and the character "b" indicates the number of bits.
Address signals to be provided in order to access a target memory cell in the memory array 101 are provided to a row decoder 102 for selecting a target row and a column decoder 103 for selecting a target column. Lines for transferring output data items from the row decoder 102 are connected to the "m" word lines 104. Only the selected word line 104 is activated in synchronism with the rising edge of a clock signal. Simultaneously, a precharge circuit 106 connected to all of the bit lines 105 enters an inactive state, so that the reset state of the bit lines 105 is released. Thereby, a small signal of the data item stored in the target memory cell is output to the bit lines 105 of (n.times.b) pairs formed in the column direction.
On the other hand, one pair of all of the bit lines 105 is selected based on the column selection signal generated by the column decoder 103. The small signal having a small voltage potential on the bit lines 105 in the selected pair "b" is inputted to corresponding "b" sense amplifiers 108. Then, the sense amplifier is activated by the sense amplifier activation signal. The small signal provided to the bit lines 105 is amplified by the sense amplifier 108 to obtain the data output signal of "b" bits of a CMOS level. The word line 104 enters the inactive state in synchronism with the falling edge of the clock signal, so that all of the memory cells 107 enter the inactive state. The precharge circuit 106 becomes the active state simultaneously, all of remained signals on the bit lines are reset. The data read out process is performed based on the operations described above.
On the contrary, in the data writein process, a writein buffer 109 corresponding to each bit line is connected to each of the bit line 105 selected by the column decode signal output from the column decoder 103. The operation timing of each bit line 105 and the word line 104 activated by the row decoder 102 is basically equal to the operation timing in the data readout operation.
Further, recently, methods to increase the operation speed by performing a parallel processing are widely and frequently used. In the systems of the parallel processing, memories having multiple ports are often used because the contents of data stored in the memory are commonly used for processes that are executing in parallel. When the memory having the multiple ports is used, there is the advantage that it is possible to avoid the occurrence of a resource conflict that reduces the performance of the system and also possible to easily control the coherent caused between units executed in parallel. In those system, to mount a high speed memory having a larger memory size on those systems leads to increase the performance of the system. Thereby, In recent years, systems incorporating a memory of a larger memory size based on the scaling of process have been developed and used.
Next, a description will be given of the operation of the conventional memory of parallel processing described above.
FIG. 3 is a diagram showing a configuration of a conventional synchronous random access memory having two ports. FIG. 4 is a timing chart of the operation of the conventional synchronous random access memory shown in FIG. 3.
In order to operate each port independently in the conventional synchronous random access memory having two ports shown in FIG. 3, all components other than the memory cell 107 in the conventional synchronous random access memory shown in FIG. 1 are incorporated in duplicate. That is, the synchronous random access memory shown in FIG. 3 comprises row decoders (A and B) 111, column decoders (A and B) 112, sense amplifiers (A and B) 113, write-in buffers (A and B) 114, precharge circuits (A and B) 115, word lines (A and B) 116, bit lines (A and B) 117 for ports A and B. These circuit components performed independently to each other corresponding to control signals for each of the ports A and B such as an address signal, a sense amplifier activation signal, and a write-in control signal. In this operation, a plurality of the memory cells 118 arranged in an array form in the memory array 119 are commonly used.
The explanation of the operation of each of the ports A and B is omitted here because this operation is the same as that of the conventional synchronous random access memory having one port shown in FIG. 1.
In the synchronous memory of the multiple-ports having the configuration shown in FIG. 3 formed by using fine process, the following drawbacks are caused: First, the delay as a result of the scaling of a memory having a fined structure is becoming smaller than the delay of the wiring. The primary reason of the change of the delay is the increasing of a RC propagation delay caused by increasing the wiring resistance. It is difficult to perform the scaling of the structure of the memory in a longitudinal direction. Thereby, the aspect ratio (a thickness of a wiring layer/ a width of the wiring layer) of the wiring becomes increased and the ratio of the thickness of the wiring layer to the thickness between adjacent layers becomes increased simultaneously. As a result, there is an increasing tendency that the magnitude of a coupling capacitance between the adjacent wiring layers becomes greater than that of the ground capacitance of the wiring. Accordingly, when a memory having multiple ports is designed by using the fine processing, there is a possibility to cause an operation error by the cross talk of signals between ports. The reason will be explained by using a conventional memory having two ports, as shown in FIG. 5.
Both the two pairs of bit lines A and /A 117, and B and /B 117 are placed in the configuration shown in FIG. 5. That is, the bit lines A and B, and /A and /b corresponding to different ports are placed so that each of the two pairs comprising the bit lines A and B and the bit lines /A and /B are adjacent to each other. In this configuration, of course, there is a possibility that the cross talk of a signal happens between the bit lines of adjacent memory cells.
As described above, when the process scaling becomes fine, the wiring capacitance between bit lines becomes greater than the ground capacitance. As shown in the timing chart of the operation of the conventional synchronous random access memory having two ports, as shown in FIG. 4, when one port enters the data readout operation and another port enters the data writein operation, the cross talk noise generated by the bit line (for example, it is operable under a CMOS voltage level, for example, 3.3 volts when the voltage of a power source is 3.3 volts) under the data writein operation is added onto the bit line under the data readout operation in which a several tens volts of a signal having a small amplitude is transferred.
In the normal operation, the bit line under the data readout operation is only discharged by a small current in a memory cell, so that this bit line has a higher impedance. Accordingly, the voltage level of the bit line used in the data readout operation is easily inverted. Temporarily, when the capacitance between the bit lines is approximately 1/3 times of the total capacitance, this cross talk noise of approximately one volt (1 V) will affect the bit line for the data readout operation. In general, because a bit line to be used for the data readout operation is accessed by a small current flowing from a memory cell, it takes a long time period to recover the data contents of the memory cells. This causes to increase the time required to the data readout operation. Furthermore, in the worst case, an output voltage level of the bit line is inverted in voltage, and thereby error operation will happen. In the prior art, in order to avoid the generation of the cross talk caused between bit lines, a power source/ground line is formed as a shield between bit liens. This method may reduce the occurrence of the cross talk approximately 10%. However, it is difficult to suppress the increasing of the time required for the data readout operation caused by the cross talk noise completely by this method, and this method causes to increase the wiring area.
The conventional drawbacks describe above are caused in a general memory of one port. When a memory array is divided into a plurality of banks, each bank performs the data readout operation and the data write-in operation independently, the cross talk noise is generated between the memory cells located at the boundary of the banks. This problem about the cross talk noise will be caused in a memory in which the data read and write operations may be performed per bit.
As described above, in the conventional memory capable of performing the data readout operation and the data write-in operation independently, the wiring capacitance between bit lines is increased by the fine processes. Thereby, when the data readout operation and the data writein operation are performed simultaneously between the adjacent bit lines, the voltage change of the bit line in the data writein operation affects the voltage change of the bit line in the data readout operation because the magnitude of the cross talk noise between bit lines is increased. In this case, the correct data items stored in the memory cells are changed. Thereby, it takes a long time period to recover the contents of the data stored in the memory cells. In addition to this drawback, the error operation is also occurred.